Comprehensive search ChatGPT Online Scientific research tools Facebook Group Tools Telegram
Sign in Sign Up

Science Hub 每 Free Research Papers | Academic Community


[IEEE] A Review on Logic Gate Design and Layout Optimization in Cadence Virtuoso for Low-Power VLSI Applications

meibei Post time 5 day(s) ago | Show all posts |Read mode
This post will be closed automatically in 2026-06-22 00:01
Reward30points

×

Create a Similar Post

journalㄩ2025 5th IEEE International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC)

AuthorsㄩBristi Hajra; Jyotishko Chakrabotry; Pradipta Dutta

Published dateㄩ2025-12-5

DOIㄩ10.1109/aespc67542.2025.11326799

PDF linkㄩhttps://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=11326799

Article linkㄩhttps://doi.org/10.1109/aespc67542.2025.11326799

Article SourceㄩIEEE﹝


Remarkㄩ

Best Answer

Conker1190 Intermediate member
5 day(s) ago
Please approve

View Full Content

You can support us by donating, we would be very grateful.
Reply

Use magic Donate Report

All Reply1 Show all posts
Conker1190 Post time 5 day(s) ago | Show all posts

This post has been completed

Completed attachments will be deleted within 24 hours.
You can support us by donating, we would be very grateful.
Reply

Use magic Donate Report

meibei Lv.3
Intermediate member

  • post

  • reply

  • points

    470

Same Category


Latest Reply

Announcement

Daily Top Contributors

Return to the list