A Floating-Point CIM Macro Featuring Asymmetric Exponent Encoding and Adaptive Mantissa Truncation for High-Efficiency AI Edge Computing

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Abstract:Floating-Point Computing-in-Memory (FP-CIM) holds significant promise for low-power AI edge computing but is limited by the dynamic range of conventional exponent encoding and the high overhead of mantissa processing. This paper presents a co-optimized architecture featuring an Asymmetric Exponent Encoding (AEE) scheme to expand dynamic range, CAM-enhanced 9T-SRAM for in-situ mantissa computation with exponent-difference-adaptive truncation(E-DAMT) , and a four-cycle sequential Binary-Coded Decimal(BCD) shifter for efficient alignment. Evaluated in 28nm CMOS simulation, the 4Kb macro occupies 0.115mm2, operates at 512MHz (0.9V), and achieves 25.9 TFLOPS/W.

Published in: 2026 IEEE International Symposium on Circuits and Systems (ISCAS)
Date of Conference: 24-28 May 2026
Date Added to IEEE Xplore: 18 June 2026
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DOI: 10.1109/ISCAS66217.2026.11562558

Conference Location: Shanghai, China

[IEEE] A Floating-Point CIM Macro Featuring Asymmetric Exponent Encoding and Adaptive Mantissa Truncation for High-Efficiency AI Edge Computing

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[IEEE] A Floating-Point CIM Macro Featuring Asymmetric Exponent Encoding and Adaptive Mantissa Truncation for High-Efficiency AI Edge Computing