[IEEE] Design of ESD Protection Circuits for LNA Using 65-nm CMOS Technology

MohdFarhan Post time 6 day(s) ago | Show all posts |Read mode
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journalㄩ2021 International Conference on Advances in Computing and Communications (ICACC)

AuthorsㄩLakshmi Nair; Karthigha Balamurugan; M Jayakumar

Published dateㄩ2021-10-21

DOIㄩ10.1109/icacc-202152719.2021.9708297

PDF linkㄩhttps://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=9708297

Article linkㄩhttps://doi.org/10.1109/icacc-202152719.2021.9708297

Article SourceㄩIEEE


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