A 41.2-to-47.8-GHz CMOS PLL With 56.3-fsrms Jitter and 75.2-dBc Reference Spur Using a Quadrature Dual-Path Phase Detector

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journal：Microelectronics Journal

Authors：Yuqian Han; Yicong Li; Yisi Yang; Xiuqiong Li; Mengding Guo; Yuan Liang; Yanan Bao; Yufan Xie; Xuanbin Jiang

Published date：2026-8-

DOI：10.1016/j.mejo.2026.107416

PDF link：https://www.sciencedirect.com/sc ... 879239126003723/pdf

Article link：https://doi.org/10.1016/j.mejo.2026.107416

Article Source：Elsevier BV。

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[Elsevier] A 41.2-to-47.8-GHz CMOS PLL With 56.3-fsrms Jitter and 75.2-dBc Reference Spur Using a Quadrature Dual-Path Phase Detector

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[Elsevier] A 41.2-to-47.8-GHz CMOS PLL With 56.3-fsrms Jitter and 75.2-dBc Reference Spur Using a Quadrature Dual-Path Phase Detector Copy

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[Elsevier] A 41.2-to-47.8-GHz CMOS PLL With 56.3-fsrms Jitter and 75.2-dBc Reference Spur Using a Quadrature Dual-Path Phase Detector