FPGA-Accelerated Risk Management for High-Frequency Trading with Two-Level Pipelined Architecture and Re-hash Tree Probing

Post time 2026-8-14 18:31:21

journal：2026 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)

Authors：Katherine Shu-Min Li; Chuan-Pu Chiou; Cheng-Han Yu; Sying-Jyan Wang; Liang-Chia Cheng; Chun-Lung Hsu; Chien-Cheng Peng; Bin-Ming Wang; Fang-Chi Wu

Published date：2026-4-13

DOI：10.1109/vlsitsa69131.2026.11527587

PDF link：https://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=11527587

Article link：https://doi.org/10.1109/vlsitsa69131.2026.11527587

Article Source：IEEE。

Remark：please help me find this paper

Post time 2026-8-14 18:31:22

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