[SPIE] Track height reduction for standard-cell in below 5nm node: how low can you go?

adi05rjn Post time 2026-8-18 00:03:15 | Show all posts |Read mode
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Edited by adi05rjn at 2026-8-18 00:03

journalㄩDesign-Process-Technology Co-optimization for Manufacturability XII

AuthorsㄩPraveen Raghavan; Vassilios Gerousis; Diederik Verkest; Anda Mocuta; Ryan Ryoung Han Kim; Alessio Spessot; Julien Ryckaert; Syed Muhammad Yasser Sherazi; Peter Debacker; Luca Mattii; Jung Kyu Chae

Published dateㄩ2018-3-20

DOIㄩ10.1117/12.2297191

Article linkㄩhttps://doi.org/10.1117/12.2297191

Article SourceㄩSPIE


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tareq932365 Post time 2026-8-18 00:03:16 | Show all posts

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