Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet

Post time 2026-8-18 00:03:34

Edited by adi05rjn at 2026-8-18 00:03

journal：Design-Process-Technology Co-optimization for Manufacturability XIII

Authors：Syed Muhammad Yasser Sherazi; Miroslav Cupak; Pieter Weckx; Odysseas Zografos; Doyoung Jang; Peter Debacker; Diederik Verkest; Anda C. Mocuta; Ryoung-Han R. Kim; Alessio Spessot; Julien Ryckaert

Published date：2019-3-27

DOI：10.1117/12.2514569

Article link：https://doi.org/10.1117/12.2514569

Article Source：SPIE。

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Post time 2026-8-18 00:03:35

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[SPIE] Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet

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