FPGA Implementation of a Fault-Tolerant Low-Latency Reversible ALU Using Hybrid Parity-Preserving IG–NFT Logic Gates in Verilog HDL

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journal：2026 4th International Conference on Intelligent Data Communication Technologies and Internet of Things (IDCIoT)

Authors：Kattubadi Abdul Raseed; S. Rambabu; Manubolu Venugopal Naidu; C. Gangaiah Yadav; Bikkili Alekya Himabindu

Published date：2026-2-4

DOI：10.1109/idciot67589.2026.11455728

PDF link：https://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=11455728

Article link：https://doi.org/10.1109/idciot67589.2026.11455728

Article Source：IEEE。

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[IEEE] FPGA Implementation of a Fault-Tolerant Low-Latency Reversible ALU Using Hybrid Parity-Preserving IG–NFT Logic Gates in Verilog HDL