[Other] A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS

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journalㄩIEICE Electronics Express

AuthorsㄩMingliang Chen; Keke Wu; Yupeng Shen; Zhiyu Wang; Hua Chen; Jiarui Liu; Faxin Yu

Published dateㄩ2021-6-10

DOIㄩ10.1587/elex.18.20210171

PDF linkㄩhttps://www.jstage.jst.go.jp/art ... 18_18.20210171/_pdf

Article linkㄩhttps://doi.org/10.1587/elex.18.20210171

Article SourceㄩInstitute of Electronics, Information and Communications Engineers (IEICE)﹝


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