Design and Implementation of a Low-Power Approximate Booth Multiplier Using Hybrid Truncation in VLSI

Post time 2026-10-16 17:17:56

journal：2026 3rd International Conference on Trends in Engineering Systems and Technologies (ICTEST)

Authors：R. Tharani; T.R. Dinesh Kumar; S. SivaSaravana Babu; Harini S; Kalaivani T; Jayasri P

Published date：2026-7-

DOI：10.1109/ictest69239.2026.11722945

PDF link：https://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=11722945

Article link：https://doi.org/10.1109/ictest69239.2026.11722945

Article Source：IEEE。

Remark：

Post time 2026-10-16 17:17:57

: This post has been completed
Completed attachments will be deleted within 24 hours.

[IEEE] Design and Implementation of a Low-Power Approximate Booth Multiplier Using Hybrid Truncation in VLSI

Best Answer

Same Category

Latest Reply

Announcement

Daily Top Contributors

[IEEE] Design and Implementation of a Low-Power Approximate Booth Multiplier Using Hybrid Truncation in VLSI Copy

Best Answer

Same Category

Latest Reply

Announcement

Daily Top Contributors

[IEEE] Design and Implementation of a Low-Power Approximate Booth Multiplier Using Hybrid Truncation in VLSI