Leakage Aware CMOS Design: A Novel Technique for Power-Constrained VLSI Systems

Post time 2026-10-17 13:47:14

journal：2026 IEEE 6th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)

Authors：Hema Bahubali Pimpale; Ramyashree H Pujari; Kirthan S Hiremath; Ashutosh Srivastava; Laxmi Jadhav

Published date：2026-6-

DOI：10.1109/vlsisata69163.2026.11610087

PDF link：https://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=11610087

Article link：https://doi.org/10.1109/vlsisata69163.2026.11610087

Article Source：IEEE。

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Post time 2026-10-17 13:47:15

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