A Power Optimized 32-Bit Carry Look Ahead Adder Employing PTL and NMOS Power Gated Technique for VLSI Circuits

Post time 2026-10-17 13:56:36

journal：2026 International Conference on Recent Advancement in Electrical, Computer and Communication Technologies (IECCT)

Authors：Padma Challa; Y. Deekshitha; Y. Sudharani; Y. Sree Latha; T. Chandana; T. Manoj Kumar

Published date：2026-4-

DOI：10.1109/iecct68664.2026.11541640

PDF link：https://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=11541640

Article link：https://doi.org/10.1109/iecct68664.2026.11541640

Article Source：IEEE。

Remark：

Post time 2026-10-17 13:56:37

: This post has been completed
Completed attachments will be deleted within 24 hours.

[IEEE] A Power Optimized 32-Bit Carry Look Ahead Adder Employing PTL and NMOS Power Gated Technique for VLSI Circuits

Best Answer

Same Category

Latest Reply

Announcement

Daily Top Contributors

[IEEE] A Power Optimized 32-Bit Carry Look Ahead Adder Employing PTL and NMOS Power Gated Technique for VLSI Circuits Copy

Best Answer

Same Category

Latest Reply

Announcement

Daily Top Contributors

[IEEE] A Power Optimized 32-Bit Carry Look Ahead Adder Employing PTL and NMOS Power Gated Technique for VLSI Circuits