A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces

Post time 2026-10-18 17:32:51

journal：IEEE Journal of Solid-State Circuits

Authors：Kahyun Kim; Daehoon Na; Jeongeun Song; Hajung Park; Jin-Seok Heo; Hyunjun Park; Jihee Kim; Hanseok Kim; Hyeri Roh; Jung-Hun Park; Woo-Seok Choi

Published date：2026-1-

DOI：10.1109/jssc.2025.3618903

PDF link：https://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=11215671

Article link：https://doi.org/10.1109/jssc.2025.3618903

Article Source：Institute of Electrical and Electronics Engineers (IEEE)。

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Post time 2026-10-18 17:32:52

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[IEEE] A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces

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