A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring

Post time 2026-10-18 17:33:44

journal：IEEE Journal of Solid-State Circuits

Authors：Junhui Gu; John Ma; Azhar Ahmed Chowdhury; Jianmin Guo; Xin Zhang; Jackson Ding; Hui Wang; Ken Chang

Published date：2025-4-

DOI：10.1109/jssc.2025.3545483

PDF link：https://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=10919466

Article link：https://doi.org/10.1109/jssc.2025.3545483

Article Source：Institute of Electrical and Electronics Engineers (IEEE)。

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Post time 2026-10-18 17:33:45

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[IEEE] A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring

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