[IEEE] FPGA-Based Hardware Accelerator for Bottleneck Residual Blocks of MobileNetV2 Convolutional Neural Networks

thien_nguyen Post time 6 day(s) ago | Show all posts |Read mode
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journalㄩ2025 IEEE 68th International Midwest Symposium on Circuits and Systems (MWSCAS)

AuthorsㄩJordi P. Mir車; Mokhles A. Mohsin; Arkan Alkamil; Darshika G. Perera

Published dateㄩ2025-8-10

DOIㄩ10.1109/mwscas53549.2025.11244457

PDF linkㄩhttps://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=11244457

Article linkㄩhttps://doi.org/10.1109/mwscas53549.2025.11244457

Article SourceㄩIEEE﹝


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