Edited by alutry at 2026-6-24 14:11
Abstract:Dual-port static random-access memory (SRAM) is often adopted to maximize data throughput for high-bandwidth applications like registers and caches. However, conventional dual-port SRAM suffers from inherent bitline leakage current and read-write disturbance issues. This work presents a highly stable dual-port 8T-SRAM macro design. The macro uses a one-sided leakage compensation circuit (LCC) module to enhance the tolerable ability of bitline leakage current. The macro uses a double pump CLK generation to achieve dual-port read and write operations through a time-sharing scheme. A read-write arbitration circuit is proposed to solve the potential read-write disturbance issues in dual-port SRAMs. Under 28 nm CMOS process, simulation results manifest the maximum tolerable leakage current is 240 米A and maximum operating frequency can reach 1.6 GHz at 0.9 V.
Published in: 2026 IEEE International Symposium on Circuits and Systems (ISCAS)
Date of Conference: 24-28 May 2026
Date Added to IEEE Xplore: 18 June 2026
ISBN Information:
ISSN Information:
DOI: 10.1109/ISCAS66217.2026.11562839
Conference Location: Shanghai, China
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Correction of Failure Data Under Electrode Disconnection for Accurate Electrical Impedance Tomography
