Abstract:This paper proposes an optimized 5-bit approximate squaring circuit-based, multiplier-free floating-point in-memory computing architecture. Via mathematical transformations, the design converts mantissa multiplication into low-cost squaring operations, eliminating conventional multipliers while retaining high computational precision. The proposed squaring circuit employs a modular combinational logic structure to minimize hardware complexity. Fabricated in a 28 nm CMOS process, the 4 Kb macro operates at 200 MHz. Under FP16 precision, simulation results show a peak energy efficiency of 21.84 TFLOPS/W, with a maximum absolute error of 0.03 and a relative error of 3.07%. These outcomes indicate that the architecture not only significantly improves energy efficiency but also offers a viable solution for high-precision floating-point computing.
Published in: 2026 IEEE International Symposium on Circuits and Systems (ISCAS)
Date of Conference: 24-28 May 2026
Date Added to IEEE Xplore: 18 June 2026
ISBN Information:
ISSN Information:
DOI: 10.1109/ISCAS66217.2026.11562926
Conference Location: Shanghai, China
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Correction of Failure Data Under Electrode Disconnection for Accurate Electrical Impedance Tomography
